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1 p/n:pm1289 rev. 1.2, mar. 06, 2009 64m-bit [4m x 16/8m x 8] cmos equal sector flash memory features general features ? 8m bytes/4m words switchable ? 128 equal sectors with 64k bytes (32k words) each - any combination of sectors can be erased with erase suspend/resume function ? single power supply operation - 2.7 to 3.6 volt for read, erase, and program operations ? latch-up protected to 100ma from -1.0v to 1.5 x vcc ? low vcc write inhibit is equal to or less than vlko ? compatible with jedec standard - pinout and software compatible to single power supply flash performance ? high performance - access time: 90ns - program time: 11us/word - erase time: 0.7s/sector, 45s/chip (typical) ? low power consumption - low active read current: 9ma (typical) at 5mhz - low standby current: 5ua(typical) ? 100,000 erase/program cycles (typical) ? 20 years data retention software features ? support common flash interface (cfi) - flash device parameters stored on the device and provide the host system to access ? erase suspend/ erase resume - suspends sector erase operation to read data from or program data to another sector which is not being erased ? status reply - data# polling & toggle bits provide detection of program and erase operation completion or not hardware features ? ready/busy (ry/by#) output - provides a hardware method of detecting program and erase operation completion ? hardware reset (reset#) input - provides a hardware method to reset the internal state machine to read mode ? acc input pin - provides accelerated program capability ? wp#/acc input - write protect (wp#) function allows protection highest or lowest sector, regardless of sector protection set - tings security ? sector protection/chip unprotect - provides sector protect function to prevent program or erase operation in the protected sector - provides chip unprotect function to allow code changes - provides temporary sector unprotect function for code changes in previously protected sector ? sector permanent lock - a unique lock bit feature allows the content to be permanently locked mx29la641d h/l
2 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l (please contact macronix sales for specifc information regarding this permanent lock feature) secured silicon sector - provides a 128-word area for code or data that can be permanently protected - once this sector is protected, it is prohibited to program or erase within the sector again package edoo * all pb-free devices are rohs compliant general description 0/ / lv d 0elw dvk phpru wkdw fdq eh rudql]hg dv 0ewhv ri elwv hdfk ru dv 0ewhv ri elwv hdfk 7khvh ghylfhv rshudwh ryhu d yrowdh udqh ri 9 wr 9 wslfdoo xvlq d 9 srhu vxsso lq - xw 7pprvqwrx.rewernv 7 0/ +/ v r q e - vwq n 7 n v r q v v vrq ww v rpqw wr w r+6 vwrqv 7 vrw rwp xv r wv - vr v wr w - vwq r vq r vx v 7v v wv q e rpp qvvwprrqrppe20vrppv 6w 2 q 2xwxw qe q qe vqv r wr vp vvwp vq :q xv w v rvvrv w qv vv wp r wv v ppr pwv rwrq w pqp wprvwxwrvvwpwpqv 7 xwrpw w rwp r rq 0rq v pprv rp q xwrpw v r wr w 7 xv rq qv wr r w rppq wr w rppq vw 7 rq vww pq xwrpw - rqwrv w rp q v xqwrqv qxq qvv qwq wpqv 6q v q w rwrqv wn px rq wp wq rwrqv vw q e qwxw wr rp r - wrqv q rw vwrv r w r wv v 6xvq rwrq rq w v vxp rwrq rwrqr 7r ewvxvwrqwwqrwvwrwrq 7 v pqxwx w w 0rq ewrq w xvq w wp wvw q rq 0rq - q wqrr 7v rw qrq rvv rv r wx rwwrq r vwvvvxwrppvrqvvqwqvrp9wr9 :w r r rqvxpwrq q qq q vrw wxv wv v ppr wqv w - e r w vw v v q rppq xqwrqv eq wvw wr pw w vwrq r vrrwrq
3 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l pin configuration symbol pin name a0~a21/a-1 address input/lsb addr (byte mode) q0~q15 16 data inputs/outputs ce0~ce2 chip enable input (cex) we# write enable input oe# output enable input reset# hardware reset pin, active low wp#/acc hardware write protect input/ hardware acceleration pin ry/by# read/busy output byte# select 8 bit or 16 bit mode vcc +3.0v single power supply vi/o output power supply (2.7v~3.6v), which is tied to vcc gnd device ground nc pin not connected internally pin description logic symbol 16 q0-q15 ry/by# a0-a21 (a-1) v i/o wp#/acc cex oe# we# reset# 22 3ohdvhfrqwdfw0dfurql[vdohviruvshfl?flqirupdwlrquhjduglqj)%*$ sdfndjhslqfrq?jxudwlrq
4 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l chip enable truth table device ce0 ce1 ce2 enabled 9,/ 9,/ 9,/ ve 9,/ 9,+ 9,/ enabled 9,/ 9,/ 9,+ enabled 9,/ 9,+ 9,+ ve 9,+ 9,/ 9,/ ve 9,+ 9,+ 9,/ enabled 9,+ 9,/ 9,+ ve 9,+ 9,+ 9,+ 1rw r 6q wrqv q q evwwr1
5 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l block diagram control input logic program/erase high voltage write state machine (wsm) state register flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15 v i/o a0-a21 vcc gnd cex oe# we# reset# wp# acc
6 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l mx29la641d sector architecture table 1. block structure sector size sector sector address a21-a15 (x8) address range (x16) address range kbytes kwords 64 6 0000000 64 6 0000001 64 6 0000010 64 6 0000011 64 6 0000100 64 6 0000101 64 6 0000110 64 6 0000111 64 6 0001000 64 6 0001001 64 6 0001010 64 6 0001011 64 6 0001100 64 6 0001101 64 6 0001110 64 6 0001111 64 6 0010000 64 6 0010001 64 6 0010010 64 6 0010011 64 6 0010100 64 6 0010101 64 6 0010110 64 6 0010111 64 6 0011000 64 6 0011001 64 6 0011010 64 6 0011011 64 6 0011100 64 6 0011101 64 6 0011110 64 6 0011111 64 6 0100000 64 6 0100001 64 6 0100010 64 6 0100011 64 6 0100100 64 6 0100101
7 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l sector size sector sector address (x8) address range (x16) address range kbytes kwords a21-a15 64 6 0100110 64 6 0100111 64 6 0101000 64 6 0101001 64 6 0101010 64 6 0101011 64 6 0101100 64 6 0101101 64 6 0101110 64 6 0101111 64 6 0110000 64 6 0110001 64 6 0110010 64 6 0110011 64 6 0110100 64 6 0110101 64 6 0110110 64 6 0110111 64 6 0111000 64 6 0111001 64 6 0111010 64 6 0111011 64 6 0111100 64 6 0111101 64 6 0111110 64 6 0111111 64 6 1000000 64 6 1000001 64 6 1000010 64 6 1000011 64 6 1000100 64 6 1000101 64 6 1000110 64 6 1000111 64 6 1001000 64 6 1001001 64 6 1001010 64 6 1001011 64 6 1001100 64 6 1001101
8 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l sector size sector sector address a21-a15 (x8) address range (x16) address range kbytes kwords 64 6 1001110 64 6 1001111 64 6 1010000 64 6 1010001 64 6 1010010 64 6 1010011 64 6 1010100 64 6 1010101 64 6 1010110 64 6 1010111 64 6 1011000 64 6 1011001 64 6 1011010 64 6 1011011 64 6 1011100 64 6 1011101 64 6 1011110 64 6 1011111 64 6 1100000 64 6 1100001 64 6 1100010 64 6 1100011 64 6 1100100 64 6 1100101 64 6 1100110 64 6 1100111 64 6 1101000 64 6 1101001 64 6 1101010 64 6 1101011 64 6 1101100 64 6 1101101 64 6 1101110 64 6 1101111 64 6 1110000 64 6 1110001 64 6 1110010 64 6 1110011 64 6 1110100 64 6 1110101
9 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l sector size sector sector address a21-a15 (x8) address range (x16) address range kbytes kwords 64 6 1110110 64 6 1110111 64 6 1111000 64 6 1111001 64 6 1111010 64 6 1111011 64 6 1111100 64 6 1111101 64 6 1111110 64 6 1111111
10 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l legend: l=logic low=vil, h=logic high=vih, vhv=10.0 0.5v, x=don't care, ain=address in, din=data in, dout=data out notes: 1. through programming equipment, the sector protect and chip unprotect functions can also be implemented. 2. if wp#=l, all sectors are protected. if wp# remove to h, all sectors recover previous protected or unprotected status, determined by "sector protect" or "chip unprotect" function. 3. by following the requests of command sequence, sector protection, or data polling algorithm, q0~q15 would be data input or data output. 4. in word mode, a21~a0 are address pins. in byte mode a21~a-1 are address pins. in both modes, a21~a15 are sector address. 0r6w reset# cex we# oe# gguhvv q8~q15 dwd2 q0~q7 wp#/ acc rug byte device reset l x x x x highz highz highz l/h standby mode vcc 0.3v disable x x x highz highz highz h output disable h enable h h x highz highz highz l/h read mode h enable h l ain dout q8~q15 =highz dout l/h write (program/erase) h enable l h ain note 3 q8~q15 =highz note 3 note 2 accelerate program h enable l h ain note 3 q8~q15 =highz note 3 vhv temporary sector unprotect vhv x x x ain note 3 highz note 3 note 2 sector protect (note 2) vhv enable l h sector address, a6=l, a1=h,a0=l x x note 3 h chip unprotect (note 2) vhv enable l h sector address, a6=h, a1=h,a0=l x x note 3 h table 2-1. bus operation bus operation
11 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l legend: l=logic low=vil, h=logic high=vih, sa=sector address, x=don't care. notes: 1. sector unprotected code: 00h, sector protected code:01h. 2. factory locked code: for 29la641dl: 88h. for 29la641dh: 98h. factory unlocked code: for 29la641dl: 08h. for 29la641dh: 18h. description control input a21 to a15 a14 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 q8 to q15 q7 to q0 cex oe# we# sector lock status verifcation enable l h sa x vhv x l x l h l x note 1 read indicator bit(q7) for security sector enable l h x x vhv x l x l h h x note 2 read manufacturer id enable l h x x vhv x l x l l l 00 c2h read device id--- 1st cycle enable l h x x vhv x l x l l h 22 7eh 2nd cycle h h l 22 13h 3rd cycle 641dh h h h 22 01h 641dl h h h 22 00h table 2-2. bus operation
12 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l write commands/command sequences to write a command to the device, system must drive we# and cex to vil, and oe# to vih. in a command cycle, all address are latched at the later falling edge of cex and we#, and all data are latched at the earlier rising edge of ce# and we#. figure 1 illustrates the ac timing waveform of a write command, and table 3 defnes all the valid command sets of the device. system is not allowed to write invalid commands not defned in this datasheet. writing an invalid command will bring the device to an undefned state. requirements for reading array data read array action is to read the data stored in the array. while the memory device is in powered up or has been reset, it will automatically enter the status of read array. if the microprocessor wants to read the data stored in the array, it has to drive cex (device enable control pin) and oe# (output control pin) as vil, and input the address of the data to be read into address pin at the same time. after a period of read cycle (tce or taa), the data being read out will be displayed on output pin for microprocessor to access. if cex or oe# is vih, the output will be in tri-state, and there will be no data displayed on output pin at all. after the memory device completes embedded operation (automatic erase or program), it will automatically re - turn to the status of read array, and the device can read the data in any address in the array. in the process of erasing, if the device receives the erase suspend command, erase operation will be stopped temporarily after a period of time no more than tready and the device will return to the status of read array. at this time, the device can read the data stored in any address except the sector being erased in the array. in the status of erase sus - pend, if user wants to read the data in the sectors being erased, the device will output status data onto the out - put. similarly, if program command is issued after erase suspend, after program operation is completed, system can still read array data in any address except the sectors to be erased. the device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. in program or erase operation, the programming or erasing failure causes q5 to go high. 2. the device is in auto select mode or cfi mode. in the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data. accelerated program operation the accelerated program can improve programming performance compared with word/byte program. by apply - ing vhv on wp#/acc pin, the device will enter accelerated program and draw current no more than iacc from wp#/acc pin. removing the vhv from wp#/acc pin will put the device back to normal operation (not acceler - ated).
13 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l reset# operation driving reset# pin low for a period more than trp will reset the device back to read mode. if the device is in program or erase operation, the reset operation will take at most a period of tready for the device to return to read array mode. before the device returns to read array mode, the ry/by# pin remains low (busy status). when reset# pin is held at gnd 0.3v, the device consumes standby current(isb).however, device draws larg - er current if reset# pin is held at vil but not within gnd 0.3v. it is recommended that the system to tie its reset signal to reset# pin of fash memory, so that the fash memo - ry will be reset during system reset and allows system to read the boot-up frware from fash memory. sector protect operation when a sector is protected, program or erase operation will be disabled on these sectors. mx29la641d h/l pro - vides two methods for sector protection. once the sector is protected, the sector remains protected until next chip unprotect, or is temporarily unprotected by asserting reset# pin at vhv. refer to temporary sector unprotect operation for further details. the frst method is by applying vhv on reset# pin. refer to figure 14 for timing diagram and figure 15 for the algorithm for this method. the other method is asserting vhv on a9 and oe# pins, with a6 and cex at vil. the protection operation begins at the falling edge of we# and terminates at the rising edge. contact macronix for details. chip unprotect operation mx29la641d h/l provides two methods for chip unprotect. the chip unprotect operation unprotects all sec - tors within the device. it is recommended to protect all sectors before activating chip unprotect mode. all sectors groups are unprotected when shipped from the factory. the frst method is by applying vhv on reset# pin. refer to figure 14 for timing diagram and figure 15 for al - gorithm of the operation. the other method is asserting vhv on a9 and oe# pins, with a6 at vih and ce# at vil (see table 2). the unpro - tect operation begins at the falling edge of we# and terminates at the rising edge. contact macronix for details. temporary sector unprotect operation system can apply reset# pin at vhv to place the device in temporary unprotect mode. in this mode, previously protected sectors can be programmed or erased just as it is unprotected. the devices returns to normal opera - tion once vhv is removed from reset# pin and previously protected sectors are again protected.
14 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l write protect (wp#) this write protect function provides a hardware protection method to protect all sectors without using vhv. by driving the wp#/acc pin low, the device disable program and erase function in all sectors. if the wp#/acc is held high (vih to vcc), these sectors revert to their previous protected/unprotected status. automatic select operation when the device is in read array mode, erase-suspended read array mode or cfi mode, user can issue read silicon id command to enter read silicon id mode. after entering read silicon id mode, user can query several silicon ids continuously and does not need to issue read silicon id mode again. in read silicon id mode, issuing reset command will reset device back to read array mode or erase-suspended read array mode. mx29la641d h/l provides hardware method to access the silicon id read operation. which method requires vhv on a9 pin, vil on cex, oe# and a6 pins. which apply a1=vil, a0=vil, the device will output mxic's manufac - ture code of c2h. which apply a1=vil, a0=vih, the device will output device code of 227eh. table 2 shows the sequence for reading mx29la641d h/l device codes. verify sector protect status operation mx29la641d h/l provides hardware sector protection against program and erase operation for protected sec - tors. the sector protect status can be read through sector protect verify command. this method requires vhv on a9 pin, vih on we# and a1 pins, vil on cex, oe#, a6 and a0 pins, and sector address on a15 to a21 pins. if the read out data is 01h, the designated sector is protected. oppositely, if the read out data is 00h, the designated sector is not protected. security sector flash memory region the security sector region is an extra otp memory space of 128 words in length. the security sectors can be locked upon shipping from factory, or it can be locked by customer after shipping. customer can issue security sector factory protect verify and/or security sector protect verify to query the lock status of the device. in factory-locked device, security sector region is protected when shipped from factory and the security silicon sector indicator bit is set to "1". in customer lockable device, security sector region is unprotected when shipped from factory and the security silicon indicator bit is set to "0". factory locked: security sector programmed and protected at the factory in a factory locked device, the security silicon region is permanently locked after shipping from factory. the de - vice will have a 16-byte (8-word) esn in the security region at address : 000000h - 000007h. the secured silicon sector address space in this device is allocated as follows. secured silicon sector address range standard factory locked express flash factory locked customer lockable 000000h-000007h esn esn or determined by customer determined by customer 000008h-00007fh unavailable determined by customer
15 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l customer lockable: security sector not programmed or protected at the factory when the security feature is not required, the security region can act as an extra memory space. security silicon sector can also be protected by two methods. note that once the security silicon sector is pro - tected, there is no way to unprotect the security silicon sector and the content of it can no longer be altered. the frst method is to write a three-cycle command of enter security region, and then follow the sector protect algorithm as illustrated in figure 15, except that reset# pin may at either vih or vhv. the other method is to write a three-cycle command of enter security region, and then follow the alternate method of sector protect with a9, oe# at vhv. after the security silicon is locked and verifed, system must write exit security sector region, go through a pow - er cycle, or issue a hardware reset to return the device to read normal array mode. data protection to avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. besides, only after successful completion of the specifed command sets will the device begin its erase or program operation. other features to protect the data from accidental alternation are described as followed. low vcc write inhibit the device refuses to accept any write command when vcc is less than vlko. this prevents data from spuri - ously altered. the device automatically resets itself when vcc is lower than vlko and write cycles are ignored until vcc is greater than vlko. system must provide proper signals on control pins after vcc is larger than vlko to avoid unintentional program or erase operation write pulse "glitch" protection cex, we#, oe# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. logical inhibit a valid write cycle requires both cex and we# at vil with oe# at vih. write cycle is ignored when either cex at vih, we# a vih, or oe# at vil. power-up sequence upon power up, mx29la641d h/l is placed in read array mode. furthermore, program or erase operation will begin only after successful completion of specifed command sequences.
16 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l power-up write inhibit when we#, cex is held at vil and oe# is held at vih during power up, the device ignores the frst command on the rising edge of we#. power supply decoupling a 0.1uf capacitor should be connected between the vcc and gnd to reduce the noise effect.
17 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l software command definitions table 3 indicates all valid command sequences. please note that if you give wrong address and data, or write them by wrong command sequence, the device will be reset into read mode. while we# or cex goes low, the falling edge of which happens later will latch all address. while we# or cex goes high, and the rising edge of which happens frst will latch all data. table 3. mx29la641d h/l command definitions command read mode reset mode automatic select manufacturer id device id security sector factory protect verify sector protect verify word byte word byte word byte word byte 1st bus cycle addr addr xxx 555 aaa 555 aaa 555 aaa 555 aaa data data f0 aa aa aa aa aa aa aa aa 2nd bus cycle addr 2aa 555 2aa 555 2aa 555 2aa 555 data 55 55 55 55 55 55 55 55 3rd bus cycle addr 555 aaa 555 aaa 555 aaa 555 aaa data 90 90 90 90 90 90 90 90 4th bus cycle addr x00 x00 x01 x02 x03 x06 (sector) x02 (sector) x04 data c2h c2h id1 id1 98/18 (h) 88/08 (l) 98/18 (h) 88/08 (l) 00/01 00/01 5th bus cycle addr x0e x1c data id2 id2 6th bus cycle addr x0f x1e data id3 id3 command enter security sector region enable exit security sector program chip erase sector erase cfi read erase suspend erase resume word byte word byte word byte word byte word byte word byte byte/word byte/word 1st bus cycle addr 555 aaa 555 aaa 555 aaa 555 aaa 555 aaa 55 aa xxx xxx data aa aa aa aa aa aa aa aa aa aa 98 98 b0 30 2nd bus cycle addr 2aa 555 2aa 555 2aa 555 2aa 555 2aa 555 data 55 55 55 55 55 55 55 55 55 55 3rd bus cycle addr 555 aaa 555 aaa 555 aaa 555 aaa 555 aaa data 88 88 90 90 a0 a0 80 80 80 80 4th bus cycle addr xxx xxx addr addr 555 aaa 555 aaa data 00 00 data data aa aa aa aa 5th bus cycle addr 2aa 555 2aa 555 data 55 55 55 55 6th bus cycle addr 555 aaa sec- tor sec- tor data 10 10 30 30 notes: device id id1 id2 id3 interface word byte word byte word byte MX29LA641DH 227e 7e 2213 13 2201 01 mx29la641dl 227e 7e 2213 13 2200 00
18 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l reset in the following situations, executing reset command will reset device back to read array mode: ? among erase command sequence (before the full command set is completed) ? sector erase time-out period ? erase fail (while q5 is high) ? among program command sequence (before the full command set is completed, erase-suspended program included) ? program fail (while q5 is high, and erase-suspended program fail is included) ? read silicon id mode ? sector protect verify ? cfi mode while device is at the status of program fail or erase fail (q5 is high), user must issue reset command to reset device back to read array mode. while the device is in read silicon id mode, sector protect verify or cfi mode, user must issue reset command to reset device back to read array mode. when the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ig - nore reset command. automatic select command sequence automatic select mode is used to access the manufacturer id, device id and to verify whether or not secured silicon is locked and whether or not a sector is protected. the automatic select mode has four command cycles. the frst two are unlock cycles, and followed by a specifc command. the fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. the reset command is necessary to exit the automatic select mode and back to read array. the following table shows the identifcation code with corresponding address. there is an alternative method to that shown in table 2, which is intended for eprom programmers and requires vhv on address bit a9. identifer code word/byte mode address data (hex) representation manufacturer id word x00 c2 byte x00 c2 device id, cycle 1 word x01 227e byte x02 7e device id, cycle 2 word x0e 2213 byte x1c 13 device id, cycle 3 word x0f 2201/2200 29la641d h/l byte x1e 01/00 secured silicon word x03 98/18 (h) 88/08 (h) factory locked/unlocked byte x06 98/18 (h) 88/08 (h) factory locked/unlocked sector protect verify word (sector address) x 02 00/01 unprotected/protected byte (sector address) x 04 00/01 unprotected/protected
19 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l automatic programming the mx29la641d h/l can provide the user program function by the form of byte-mode or word-mode. as long as the users enter the right cycle defned in the table.3 (including 2 unlock cycles and a0h), any data user inputs will automatically be programmed into the array. once the program function is executed, the internal write state controller will automatically execute the algo - rithms and timings necessary for program and verifcation, which includes generating suitable program pulse, verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not pass verifcation. meanwhile, the internal control will prohibit the programming to cells that pass verifcation while the other cells fail in verifcation in order to avoid over-programming. with the internal write state controller, the device requires the user to write the program command and data only. programming will only change the bit status from "1" to "0". that is to say, it is impossible to convert the bit status from "0" to "1" by programming. meanwhile, the internal write verifcation only detects the errors of the "1" that is not successfully programmed to "0". any command written to the device during programming will be ignored except hardware reset, which will termi - nate the program operation after a period of time no more than tready. when the embedded program algorithm is complete or the program operation is terminated by hardware reset, the device will return to the reading array data mode. the typical chip program time at room temperature of the mx29la641d h/l is less than 45 seconds. when the embedded program operation is on going, user can confrm if the embedded operation is fnished or not by the following methods: status q7 q6 q5 ry/by#*2 in progress*1 q7# toggling 0 0 finished q7 stop toggling 0 1 exceed time limit q7# toggling 1 0 *1: the status "in progress" means both program mode and erase-suspended program mode. *2: ry/by# is an open drain output pin and should be weakly connected to vdd through a pull-up resistor. *3: when an attempt is made to program a protected sector, q7 will output its complement data or q6 continues to toggle for about 1us or less and the device returns to read array state without programing the data in the pro - tected sector.
20 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l sector erase sector erase is to erase all the data in a sector with "1" and "0" as all "1". it requires six command cycles to is - sue. the frst two cycles are "unlock cycles", the third one is a confguration cycle, the fourth and ffth are also "unlock cycles" and the sixth cycle is the sector erase command. after the sector erase command sequence is issued, there is a time-out period of 50us counted internally. during the time-out period, additional sector ad - dress and sector erase command can be written multiply. once user enters another sector erase command, the time-out period of 50us is recounted. if user enters any command other than sector erase or erase suspend dur - ing time-out period, the erase command would be aborted and the device is reset to read array condition. the number of sectors could be from one sector to all sectors. after time-out period passing by, additional erase com - mand is not accepted and erase embedded operation begins. during sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can check the status as chip erase. when the embedded chip erase operation is on going, user can confrm if the embedded operation is fnished or not by the following methods: status q7 q6 q5 q2 ry/by# in progress 0 toggling 0 toggling 0 finished 1 stop toggling 0 1 1 exceed time limit 0 toggling 1 toggling 0 chip erase chip erase is to erase all the data with "1" and "0" as all "1". it needs 6 cycles to write the action in, and the frst two cycles are "unlock" cycles, the third one is a confguration cycle, the fourth and ffth are also "unlock" cycles, and the sixth cycle is the chip erase operation. during chip erasing, all the commands will not be accepted except hardware reset or the working voltage is too low that chip erase will be interrupted. after chip erase, the chip will return to the state of read array. *1: the status q3 is the time-out period indicator. when q3=0, the device is in time-out period and is acceptible to another sector address to be erased. when q3=1, the device is in erase operation and only erase suspend is valid. *2: ry/by# is open drain output pin and should be weakly connected to vdd through a pull-up resistor. *3: when an attempt is made to erase a protected sector, q7 will output its complement data or q6 continues to toggle for 100us or less and the device returned to read array status without erasing the data in the protected sector. when the embedded erase operation is on going, user can confrm if the embedded operation is fnished or not by the following methods: status q7 q6 q5 q3 q2 ry/by#*2 time-out period 0 toggling 0 0 toggling 0 in progress 0 toggling 0 1 toggling 0 finished 1 stop toggling 0 1 1 1 exceed time limit 0 toggling 1 1 toggling 0
21 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l when the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon id, sector protect verify, program, cfi query and erase resume. sector erase resume sector erase resume command is valid only when the device is in erase suspend state. after erase resume, user can issue another erase suspend command, but there should be a 4ms interval between erase resume and the next erase suspend. if user issue infnite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for erasing will increase. status q7 q6 q5 q3 q2 ry/by# erase suspend read in erase suspended sector 1 no toggle 0 n/a toggle 1 erase suspend read in non-erase suspended sector data data data data data 1 erase suspend program in non-erase suspended sector q7# toggle 0 n/a n/a 0 sector erase suspend during sector erasure, sector erase suspend is the only valid command. if user issue erase suspend command in the time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erase-suspended read array mode. if user issue erase suspend command during the sector erase is be - ing operated, device will suspend the ongoing erase operation, and after the tready1 (<=20us) suspend fnishes and the device will enter erase-suspended read array mode. user can judge if the device has fnished erase sus - pend through q6, q7, and ry/by#. after device has entered erase-suspended read array mode, user can read other sectors not at erase suspend by the speed of taa; while reading the sector in erase-suspend mode, device will output its status. user can use q6 and q2 to judge the sector is erasing or the erase is suspended.
22 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l table 4-1. cfi mode: identifcation data values (all values in these tables are in hexadecimal) table 4-2. cfi mode: system interface data values query command and common flash interface (cfi) mode mx29la641d h/l features cfi mode. host system can retrieve the operating characteristics, structure and vendor-specifed information such as identifying information, memory size, byte/word confguration, operating voltages and timing information of this device by cfi mode. the device enters the cfi query mode when the system writes the cfi query command "98h" to address "55h" any time the device is ready to read array data. the system can read cfi information at the addresses given in table 4. a reset command is required to exit cfi mode and go back to ready array mode or erase suspend mode. the system can write the cfi query command only when the device is in read mode, erase suspend, standby mode or automatic select mode. description address (h) (word mode) address (h) (byte mode) data (h) query-unique ascii string "qry" 10 20 0051 11 22 0052 12 24 0059 primary vendor command set and control interface id code 13 26 0002 14 28 0000 address for primary algorithm extended query table 15 2a 0040 16 2c 0000 alternate vendor command set and control interface id code 17 2e 0000 18 30 0000 address for alternate algorithm extended query table 19 32 0000 1a 34 0000 description address (h) (word mode) address (h) (byte mode) data (h) vcc supply minimum program/erase voltage 1b 36 0027 vcc supply maximum program/erase voltage 1c 38 0036 vpp supply minimum program/erase voltage 1d 3a 0000 vpp supply maximum program/erase voltage 1e 3c 0000 typical timeout per single word/byte write, 2 n us 1f 3e 0004 typical timeout for maximum-size buffer write, 2 n us 20 40 0000 typical timeout per individual block erase, 2 n ms 21 42 000a typical timeout for full chip erase, 2 n ms 22 44 0000 maximum timeout for word/byte write, 2 n times typical 23 46 0005 maximum timeout for buffer write, 2 n times typical 24 48 0000 maximum timeout per individual block erase, 2 n times typical 25 4a 0004 maximum timeout for chip erase, 2 n times typical 26 4c 0000
23 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l table 4-3. cfi mode: device geometry data values description address (h) (word mode) address (h) (byte mode) data (h) device size = 2 n in number of bytes 27 4e 0017 flash device interface description (02=asynchronous x8/x16) 28 50 0002 29 52 0000 maximum number of bytes in buffer write = 2 n (not support) 2a 54 0000 2b 56 0000 number of erase regions within device 2c 58 0001 index for erase bank area 1 [2e,2d] = # of same-size sectors in region 1-1 [30, 2f] = sector size in multiples of 256-bytes 2d 5a 007f 2e 5c 0000 2f 5e 0000 30 60 0001 index for erase bank area 2 31 62 0000 32 64 0000 33 66 0000 34 68 0000 index for erase bank area 3 35 6a 0000 36 6c 0000 37 6e 0000 38 70 0000 index for erase bank area 4 39 72 0000 3a 74 0000 3b 76 0000 3c 78 0000
24 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l table 4-4. cfi mode: primary vendor-specifc extended query data values description address (h) (word mode) address (h) (byte mode) data (h) query - primary extended table, unique ascii string, pri 40 80 0050 41 82 0052 42 84 0049 major version number, ascii 43 86 0031 minor version number, ascii 44 88 0033 unlock recognizes address (0= recognize, 1= don't recognize) 45 8a 0000 erase suspend (2= to both read and program) 46 8c 0002 sector protect (n= # of sectors/group) 47 8e 0004 temporary sector unprotect (1=supported) 48 90 0001 sector protect/chip unprotect scheme 49 92 0004 simultaneous r/w operation (0=not supported) 4a 94 0000 burst mode (0=not supported) 4b 96 0000 page mode (0=not supported) 4c 98 0000 minimum acceleration supply (0= not supported), [d7:d4] for volt, [d3:d0] for 100mv 4d 9a 0095 maximum acceleration supply (0= not supported), [d7:d4] for volt, [d3:d0] for 100mv 4e 9c 00a5 low/high boot block indicator 04h=low boot device, 05h=high boot device 4f 9e 0004/0005
25 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l absolute maximum stress ratings operating temperature and voltage note: 1. minimum voltage may undershoot to -2v during transition and for less than 20ns during transitions. 2. maximum voltage may overshoot to vcc+2v during transition and for less than 20ns during transitions. surrounding temperature with bias -65 o c to +125 o c storage temperature -65 o c to +150 o c voltage range vcc -0.5v to +4.0 v reset#, a9, acc and oe# -0.5v to +10.5 v the other pins. -0.5v to vcc +0.5v output short circuit current (less than one second) 200 ma commercial (c) grade surrounding temperature (t a ) 0c to +70c industrial (i) grade surrounding temperature (t a ) -40c to +85c vcc supply voltages vcc range +2.7 v to 3.6 v
26 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l dc characteristics symbol description min typ max remark iilk input leak r 1.0ua iilk9 a9 leak 35ua a9=10v iolk output leak 1.0ua icr1 read current (5mhz) 9ma 16ma ce#=vil, oe#=vih icr2 read current (1mhz) 2ma 4ma ce#=vil, oe#=vih icw write current 26ma 30ma ce#=vil, oe#=vih, we#=vil isb standby current 5ua 15ua vcc=vcc max, other pin disable isbr reset current 5ua 15ua vcc=vccmax, reset# enable, other pin disable isbs sleep mode current 5ua 15ua icp1 accelerated pgm current, wp#/acc pin (word/byte) 5ma 10ma ce#=vil, oe#=vih, icp2 accelerated pgm current, vcc pin (word/byte) 15ma 30ma ce#=vil, oe#=vih, vil input low voltage -0.5v 0.8v vih input high voltage 0.7xvcc vcc+0.3v vhv very high voltage for hardware protect/unprotect/auto select/ temporary unprotect/accelerated program 9.5v 10.5v vol output low voltage 0.45v iol=4.0ma voh1 ouput high voltage 0.85xvcc ioh1=-2ma voh2 ouput high voltage vcc-0.4v ioh2=-100ua vlko low vcc lock-out voltage 2.3v 2.5v
27 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l switching test circuits test condition output load : 1 ttl gate output load capacitance,cl : 30pf rise/fall times : 5ns in/out reference levels :1.5v input pulse level : 0.0 ~ 3.0v switching test waveforms 1.5v 1.5v test points 3.0v 0.0v output input r1=6.2k ohm r2=2.7k ohm tested device diodes=in3064 or equivalent cl r1 vcc 0.1uf r2 +3.3v
28 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l ac characteristics symbol description min typ max unit taa valid data output after address 90 ns tce valid data output after cex low 90 ns toe valid data output after oe# low 30 ns tdf data output foating after oe# high 30 ns toh output hold time from the earliest rising edge of address,cex, oe# 0 ns trc read period time 90 ns twc write period time 90 ns tcwc command write period time 90 ns tas address setup time 0 ns tah address hold time 45 ns tds data setup time 45 ns tdh data hold time 0 ns tvcs vcc setup time 100 us tcs chip enable setup time 0 ns tch chip enable hold time 0 ns toes output enable setup time 0 ns toeh output enable hold time read 0 ns toggle & data# polling 10 ns tws we# setup time 0 ns twh we# hold time 0 ns tcep cex pulse width 45 ns tceph cex pulse width high 30 ns twp we# pulse width 35 ns twph we# pulse width high 30 ns tbusy program/erase active time by ry/by# 90 ns tghwl read recover time before write 0 ns tghel read recover time before write 0 ns twhwh1 program operation 11 us twhwh1 acc program operation (word/byte) 7 us twhwh2 sector erase operation 0.7 sec tbal sector add hold time 50 us
29 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 1. command write operation addresses cex oe# we# din tds ta h data tdh tcs tch tcwc twph twp toes ta s disable enable vih vil vih vil vih vil vih vil va va: valid address
30 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l read/reset operation figure 2. read timing waveforms addresses cex oe# ta a we# disable enable vih vil vih vil vih vil voh vol high z high z data valid to e toeh tdf tce trc outputs to h add valid
31 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 3. reset# timing waveform ac characteristics item description setup speed unit trp1 reset# pulse width (during automatic algorithms) min 10 us trp2 reset# pulse width (not during automatic algorithms) min 500 ns trh reset# high time before read min 50 ns trb1 ry/by# recovery time (to ce#, oe# go low) min 0 ns trb2 ry/by# recovery time (to we# go low) min 50 ns tready1 reset# pin low (during automatic algorithms) to read or write max 20 us tready2 reset# pin low (not during automatic algorithms) to read or write max 500 ns trh trb1 trp2 trp1 tready2 tready1 ry/by# cex, oe# reset# reset timing not during automatic algorithms reset timing during automatic algorithms ry/by# cex, oe# trb2 we# reset#
32 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l erase/program operation figure 4. automatic chip erase timing waveform twc address oe# cex 55h 2aah sa 10h in progress complete va va ta s ta h sa: 555h for chip erase tghwl tch disable enable twp tds tdh twhwh2 read status last 2 erase command cycle tbusy trb tcs twph we# data ry/by#
33 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 5. automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no data=ffh ? write data 10h address 555h write data 55h address 2aah data# polling algorithm or toggle bit algorithm auto chip erase completed
34 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 6. automatic sector erase timing waveform twc address oe# cex 55h 2aah sector address 1 sector address 0 30h in progress complete va va 30h sector address n ta s ta h tbal tghwl tch twp disable enable tds tdh twhwh2 read status last 2 erase command cycle tbusy trb tcs twph we# data ry/by# 30h
35 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 7. automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h write data 30h sector address write data 55h address 2aah data# polling algorithm or toggle bit algorithm auto sector erase completed no last sector to erase yes yes no data=ffh
36 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 8. erase suspend/resume flowchart start write data b0h toggle bit checking q6 not toggled erase suspend yes no write data 30h continue erase reading or programming end read array or program another erase suspend ? no yes yes no erase resume
37 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 9. secured silicon sector protected algorithms flowchart start enter secured silicon sector data = 01h ? no yes wait 1us first wait cycle data=60h second wait cycle data=60h a6=0, a1=1, a0=0 wait 300us write reset command device failed secured sector protect complete
38 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 10. automatic program timing waveforms figure 11. accelerated program timing diagram address oe# cex a0h 555h pa pd status dout va va ta s ta h tghwl tch twp tds tdh twhwh1 last 2 read status cycle last 2 program command cycle tbusy trb tcs disable enable twph we# data ry/by# wp#/acc 250ns 250ns vhv (9.5v ~ 10.5v) vil or vih vil or vih
39 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 12. automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes read again data: program data? yes auto program completed data# polling algorithm or toggle bit algorithm next address last word to be programed no no
40 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 13. cex controlled write timing waveform address oe# cex a0h 555h pa pd status dout va va ta s ta h tghwl tcep disable enable tds tdh twhwh1 or twhwh2 tbusy trb tceph we# data ry/by#
41 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l sector protect/chip unprotect figure 14. sector protect/chip unprotect waveform (reset# control) 150us: sector protect 15ms: chip unprotect 1us disable enable vhv vih data sa, a6 a1, a0 cex we# oe# va va va status va: valid address 40h 60h 60h verification reset#
42 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 15-1. in-system sector protect with reset#=vhv start retry count=0 reset#=vhv wait 1us write sector address with [a6,a1,a0]:[0,1,0] data: 60h write sector address with [a6,a1,a0]:[0,1,0] data: 40h read at sector address with [a6,a1,a0]:[0,1,0] wait 150us reset plscnt=1 temporary unprotect mode reset#=vih write reset cmd sector protect done device fail temporary unprotect mode set up sector address retry count +1 first cmd=60h? data=01h? retry count=25? yes yes yes yes no no no no protect another sector?
43 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 15-2. chip unprotect algorithms with reset#=vhv write [a6,a1,a0]:[1,1,0] data: 60h write [a6,a1,a0]:[1,1,0] data: 40h read [a6,a1,a0]:[1,1,0] wait 15ms temporary unprotect reset#=vih write reset cmd chip unprotect done retry count +1 device fail all sectors protected? data=00h? last sector verified? retry count=1000? yes yes yes no no no yes protect all sectors start retry count=0 reset#=vhv wait 1us temporary unprotect first cmd=60h? yes no no
44 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 16. sector protect timing waveform (a9, oe# control) ac characteristics to e data oe# we# 10v 3v 10v 3v a9 a1 a6 toesp twpp1 tvlht tvlht tvlht verify 01h f0h a21-a15 sector address cex disable enable parameter description test setup all speed options unit tvlht voltage transition time min. 4 us twpp1 write pulse width for sector protect min. 100 ns twpp2 write pulse width for chip unprotect min. 100 ns toesp oe# setup time to we# active min. 4 us
45 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 17. sector protection algorithm (a9, oe# control) start set up sector addr plscnt=1 sector protection complete data=01h? yes . oe#=vhv, a9=vhv, cex=vil a6=vil activate we# pulse time out 150us set we#=vih, cex=oe#=vil a9 should remain vhv read from sector addr=sa, a1=1 protect another sector? remove vhv from a9 write reset command device failed plscnt=32? yes no no
46 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 18. chip unprotect timing waveform (a9, oe# control) to e data oe# we# 10v 3v 10v 3v a9 a1 toesp twpp2 tvlht tvlht tvlht verify 00h a6 f0h cex disable enable
47 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 19. chip unprotect flowchart (a9, oe# control) start protect all sectors plscnt=1 chip unprotect complete data=00h? yes set oe#=a9=vhv cex=vil, a6=1 activate we# pulse time out 15ms set oe#=cex=vil a9=vhv, a1=1 set up first sector addr all sectors have been verified? remove vhv from a9 write reset command device failed plscnt=1000? no increment plscnt no read data from device yes yes no increment sector addr * it is recommended before unprotect whole chip, all sectors should be protected in advance.
48 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 20. temporary sector unprotect waveforms ac characteristics reset# cex we# ry/by# trpvhh 10v vhv 0 or vih vil or vih tvhhwl disable enable trpvhh program or erase command sequence parameter alt description condition speed unit trpvhh tvidr reset# rise time to vhv and vhv fall time to reset# min 500 ns tvhhwl trsp reset# vhv to we# low min 4 us
49 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 21. temporary sector unprotect flowchart start apply reset# pin vhv volt enter program or erase mode (1) remove vhv volt from reset# (2) reset# = vih completed temporary sector unprotected mode mode operation completed notes: 1. temporary unprotect all protected sectors vhv=9.5~10.5v. 2. after leaving temporary unprotect mode, the previously protected sectors are again protected.
50 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 22. silicon id read timing waveform ta a ta a ta a ta a tce to e to h to h to h to h tdf data out manufacturer id device id cycle 1 device id cycle 2 device id cycle 3 vhv vih vil add a9 add cex a1 oe# we# add a0 data out data out data out data q0-q15 vcc 3v vih vil vih vil vih vil vih vil vih vil vih vil vih vil a2 disable enable
51 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l write operation status figure 23. data# polling timing waveforms (during automatic algorithms) tdf tce disable enable tch to e toeh to h cex oe# we# q7 q0-q6 ry/by# tbusy status data status data status data complement true valid data ta a trc address va va high z high z valid data true
52 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 24. data# polling algorithm read q7~q0 at valid address (note 1) read q7~q0 at valid address start q7 = data# ? q5 = 1 ? q7 = data# ? (note 2) fail pass no no no ye s ye s ye s notes: 1. for programming, valid address means program address. for erasing, valid address means erase sectors address. 2. q7 should be rechecked even q5="1" because q7 may change simultaneously with q5.
53 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 25. toggle bit timing waveforms (during automatic algorithms) tdf tce tch to e toeh ta a trc to h address oe# we# q6/q2 ry/by# tbusy valid status (first read) valid status (second read) (stops toggling) valid data va va va va : valid address va valid data disable enable cex
54 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 26. toggle bit algorithm note: 1. read toggle bit twice to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as q5 changes to "1". read q7-q0 twice q5 = 1? read q7~q0 twice program/erase fail write reset cmd program/erase complete q6 toggle ? q6 toggle ? no (note 1) yes no no yes yes start
55 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l figure 27. q6 versus q2 notes: the system can use oe# or cex to toggle q2/q6, q2 toggles only when read at an address within an erase-suspended we# enter embedded erasing erase suspend enter erase suspend program erase suspend program erase suspend read erase suspend read erase erase resume erase complete erase q6 q2
56 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l recommended operating conditions at device power-up ac timing illustrated in figure a is recommended for the supply voltages and the control signals at device power- up. if the timing in the fgure is ignored, the device may not operate correctly. figure a. ac timing at device power-up symbol parameter min. max. unit tvr vcc rise time 80 500000 us/v tr input signal rise time 20 us/v tf input signal fall time 20 us/v tvcs vcc setup time 200 us vcc address we# oe# data tvr taa tr or tf tr or tf tce tf vcc(min) gnd vih vil vih vil vih vil vih vil voh high z vol wp#/acc valid ouput valid address tvcs tr toe tf tr disable enable cex
57 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l min. max. input voltage voltage difference with gnd on wp#/acc, a9, oe#, reset# pins -1.0v 10.5v input voltage voltage difference with gnd on all i/o pins -1.0v 1.5 x vcc vcc current pulse -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. latch-up characteristics erase and programming performance parameter symbol parameter description test set typ max unit cin input capacitance vin=0 6 7.5 pf cout output capacitance vout=0 8.5 12 pf cin2 control pin capacitance vin=0 7.5 9 pf pin capacitance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0v vcc. programming specifca - tions assume checkboard data pattern. 2. maximum values are measured at vcc = 3.0 v, worst case temperature. maximum values are valid up to and including 100,000 program/erase cycles. 3. word/byte programming specifcation is based upon a single word/byte programming operation not utilizing the write buffer. 4. erase/program cycles comply with jedec jesd-47e & a117a standard. notes: 1. test conditions ta=25c, f=1.0mhz. parameter limits units min. typ.(2) max. sector erase time 0.7 2 sec chip erase time 45 65 sec word programming time 11 360 us byte programming time 9 300 us accelerated byte/word program time 7 210 us chip programming time byte mode 50 160 sec word mode 45 140 sec erase/program cycles 100,000 cycles
58 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l ordering information please contact macronix sales for specifc information regarding 64 fbga ordering information.
59 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l part name description please contact macronix sales for specifc information regarding 64 fbga part name description.
60 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l package information
61 p/n:pm1289 rev. 1.2, mar. 06, 2009 mx29la641d h/l revision history revision no. description page date 1.0 1. format changed all aug/29/2008 2. corrected wp# function description p10,11,14 3. revised sector erase time p29,58 4. changed vhv spec as 9.5v~10.5v p39 5. removed "advanced information" p1 6. revised general description p2 7. revised automatic select operation p16 8. revised software command definitions p17 1.1 1. modifed table 2-2. 2nd cycle from 1dh to 13h p11 jan/06/2008 1.2 1. modifed data retention from 10 years to 20 years p1,2 mar/06/2009
mx29la641d h/l 62 m acronix i nternational c o., l td. macronix offces : taiwan headquarters, fab2 macronix, international co., ltd. 16, li-hsin road, science park, hsinchu, taiwan, r.o.c. tel: +886-3-5786688 fax: +886-3-5632888 taipei offce macronix, international co., ltd. 19f, 4, min-chuan e. road, sec. 3, taipei, taiwan, r.o.c. tel: +886-2-2509-3300 fax: +886-2-2509-2200 macronix offces : china macronix (hong kong) co., limited. 702-703, 7/f, building 9, hong kong science park, 5 science park west avenue, sha tin, n.t. tel: +86-852-2607-4289 fax: +86-852-2607-4229 macronix (hong kong) co., limited, suzhou offce no.5, xinghai rd, suzhou industrial park, suzhou china 215021 tel: +86-512-62580888 ext: 3300 fax: +86-512-62586799 macronix (hong kong) co., limited, shenzhen offce room 1401 & 1404, blcok a, tianan hi-tech plaza tower, che gong miao, futiandistrict, shenzhen prc 518040 tel: +86-755-83433579 fax: +86-755-83438078 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifcations without notice. macronix offces : japan macronix asia limited. nkf bldg. 5f, 1-2 higashida-cho, kawasaki-ku kawasaki-shi, kanagawa pref. 210-0005, japan tel: +81-44-246-9100 fax: +81-44-246-9105 macronix offces : korea macronix asia limited. #906, 9f, kangnam bldg., 1321-4, seocho-dong, seocho-ku, 135-070, seoul, korea tel: +82-02-588-6887 fax: +82-02-588-6828 macronix offces : singapore macronix pte. ltd . 1 marine parade central, #11-03 parkway centre, singapore 449408 tel: +65-6346-5505 fax: +65-6348-8096 macronix offces : europe macronix europe n.v. koningin astridlaan 59, bus 1 1780 wemmel belgium tel: +32-2-456-8020 fax: +32-2-456-8021 macronix offces : usa macronix america, inc. 680 north mccarthy blvd. milpitas, ca 95035, u.s.a. tel: +1-408-262-8887 fax: +1-408-262-8810 macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and mili - tary application. macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of macronix's products in the prohibited applications. copyright? macronix international co., ltd. 2008~2009. all rights reserved. macronix, mxic, mxic logo, mx logo, are trademarks or registered trademarks of macronix international co., ltd.. the names and brands of other companies are for identifcation purposes only and may be claimed as the property of the respective companies.

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